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Quad SPI-3 to SPI-4 Link Layer
Lattice Semiconductor
Bridge Core User’s Guide
Polling Sequence Controller and Polling Status Table Block
Byte-Level Mode: Either the DTPA (direct transmit packet available) or STPA (selected-PHY transmit packet avail-
able) signals may be used to obtain FIFO status information from the PHY device when performing byte-level trans-
fers between the PHY and Link layers. The DTPA bus provides direct status indications for the ports in the PHY
device. There is one signal on the DTPA bus for each FIFO in the PHY. Each DTPA signal transitions high when a
prede?ned minimum number of bytes are available in the corresponding PHY Layer FIFO. The threshold at which
DTPA transitions high must be set in the PHY Layer device.
STPA may also be used to obtain FIFO status from the PHY device in byte-level transfers. STPA transitions high
when a prede?ned minimum number of bytes are available in the transmit PHY Layer FIFO speci?ed by the in-band
address on TDAT. Once high, STPA indicates the transmit FIFO is not full. When STPA transitions low, it indicates
that the transmit FIFO is full or near full. The STPA signal is used to populate the Polling Status Table which keeps
track of the latest status of each port which has been received from the PHY device.
When STPA is implemented, the Link Layer device will poll the PHY Layer FIFO before it can send data to that
FIFO. The Link Layer device will send a port number to the PHY device on TDAT, and then wait for the status of the
FIFO to be returned on STPA. Also, the Link Layer TX Interface circuit will poll the corresponding virtual FIFO in the
DPRAM to see if it contains data. When there is data in the DPRAM for a particular port number and the corre-
sponding PHY Layer FIFO has available space, then the TX Interface circuit will send a burst of data to the PHY
Layer. The TX Interface circuit will use a round-robin scheme to cycle through all ports.
If DTPA has been implemented, then polling of PHY Layer FIFOs using in-band port numbers is not needed, and
therefore the polling actions described in the previous paragraph will not be implemented. In this case the Link
device will continuously read the DPRAM FIFOs and send data in direct response to the status received on the
DTPA signals.
Packet Level Mode: The PTPA (Polled-PHY Transmit Packet Available) signal transitions high when a prede?ned
minimum number of bytes are available in the polled transmit FIFO in the PHY device. Once high, PTPA indicates
that the transmit FIFO is not full. When PTPA transitions low, it indicates that the transmit FIFO is full or near full.
PTPA allows the polling of the PHY selected by the TADR address bus. The port that PTPA reports is updated on
the following rising edge of TFCLK after the PHY address on TADR is sampled by the PHY device. The address is
driven from a counter in the Polling Sequence Controller block. This counter sequences through all of the PHY port
numbers. The Link Layer Bridge device will automatically update its internal Polling Status Table using PTPA in
response to the PHY numbers sent to the PHY on TADR.
The number of PHYs must be assigned using the NUM_PORTS parameter. Any data received from the SPI-4 that
does not have a valid PHY number will be read from the Link device’s FIFO and transmitted on the SPI-3. This pre-
vents errors in the port or PHY numbers from the SPI-4 from causing a blocking condition in the Link device
Receive Section
The receive section bridges up to four SPI-3 links to a single SPI-4. As shown in Figure 2, the receive section con-
sists of one block, the RX SPI-3 Interface. This block interfaces one SPI-3 link to as many as eight RX direction vir-
tual FIFOs within a DPRAM. There may be from one to four RX SPI-3 Interface blocks provisioned depending on
the desired number of SPI-3 links. This block receives data (32-bit bus) from the PHY device along with RSX,
REOP, RSOP, RERR and RMOD bits. All bits except RSX are written into the DPRAM. It supports either even or
odd parity checking (user programmable) over the RX data. It extracts the port address on RDAT[7:0] when indi-
cated by the RSX input being active and uses the port number to select from up to eight virtual FIFOs. The inter-
face conforms to the OIF-SPI3-01.0 speci?cation.
The port number will be indicated by the RSX signal at the beginning of a burst of data from the PHY Layer device.
For the duration of the burst, the RX SPI-3 Interface circuit writes the data into the virtual FIFO, selected by the port
number, by setting the Tx_Port[7:0] value, and it holds the RENB signal low as long as the amount of data in the
selected virtual FIFO does not exceed the threshold. For the interface to work correctly, the threshold on the
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